The semiconductor industry is producing more and more capable components with smaller and smaller feature sizes. Due to the increased demand for highly integrated semiconductor devices, advanced techniques of fabricating more semiconductor devices in a smaller die area have become strongly relied upon. The production of such semiconductor devices reveals new design and manufacturing challenges to be addressed in order to maintain or improve semiconductor device performance.
As the device density of semiconductors increases, the conductor line width and spacing within the semiconductor devices decreases. Multiple-pattern lithography represents a class of technologies developed for photolithography to enhance the feature density of semiconductor devices. Double-patterning, a subset of multiple-patterning, may be used as early as the 45 nm node in the semiconductor industry and may be the primary technique for the 32 nm node and beyond. Double-patterning employs multiple masks and photolithographic steps to create a particular level of a semiconductor device. With benefits such as tighter pitches and narrower wires, double-patterning alters relationships between variables related to semiconductor device wiring and wire quality to sustain performance.